Method and apparatus for altering data length to zero to maintain cache coherency

ABSTRACT

Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent. If there is a match, the agent copies this most recent data, changes the state of the data to unmodified, changes the length of the data to zero (for pending explicit writebacks), and performs an implicit writeback. Additionally, prior to each explicit writeback, an agent determines if the address of the explicit writeback and any incoming snoop request requests are the same. If there is a match, the agent changes the data length of the explicit writeback to zero prior to issuing the explicit writeback.

BACKGROUND

[0001] The present invention relates to an apparatus and method for animproved system of cache coherency in a multiple agent system.

[0002] In the electronic arts, a processing system may include aplurality of agents that perform coordinated computing tasks. The agentsoften share one or more main memory units designed to store addressabledata for the use of all agents. The agents communicate with the mainmemory unit and each other over a communications bus during bustransactions. A typical system is shown in FIG. 1. FIG. 1 illustrates aplurality of N agents 10, 20, 30, 40 in communication with each otherover an external communications bus 50. Data is exchanged among theagents 10, 20, 30 and the main memory unit 40 in a bus transaction.“Agents” include processors, memory units, and devices that maycommunicate over the communications bus 50.

[0003] In order to improve performance, an agent may include a pluralityof tiered internal caches that store and alter data on a temporarybasis. In such multiple agent systems, several agents may operate ondata from a single address at the same time. Multiple copies of datafrom a single memory address may be stored in multiple agents.Oftentimes when a first agent must operate on data at an address, asecond agent may store a copy of the data that is more current in itsinternal cache than the copy resident in the main memory unit 40. Inorder to maintain “cache coherency,” the first agent should read thedata from the second agent rather than from the main memory unit 40.Without a means to coordinate among agents, an agent may perform a dataoperation on a copy of data that is stale.

[0004] Along with each unit of data, an internal cache may storeadditional information, which may include the data's address in the mainmemory unit 50, the length of the data unit, and/or an indicator as towhether the data has been modified by the agent since being retrievedfrom main memory. This indicator—known as the “state” of the data—mayreflect that the data has been modified or unmodified since beingretrieved from main memory. Each agent may include cache coherencycircuitry that ensures that data in a modified state is eventuallyreturned to the main memory unit 40 via the communications bus 50.

[0005] In some agents, modified data may be returned to main memory aspart of an “explicit writeback” transaction or as part of an “implicitwriteback.” In an explicit writeback, an agent generates a bustransaction to write the modified data to external memory in order tomake room in the cache for newly requested data. That is, the agent(e.g., 10 in FIG. 1) acquires ownership of the communications bus 50 anddrives the modified data on the communications bus 50. The externalmemory (e.g., agent 40 in FIG. 1) retrieves the data from thecommunications bus 50 and stores it according to conventionaltechniques.

[0006] By contrast, an implicit writeback typically occurs as part of atransaction initiated by another agent. Consider an example where agent10 stores a copy of data in modified state; the copy in agent 10 is morecurrent than a copy stored in the main memory unit 40. If another agent20 posts a request on the communications bus 50 and requests the data,an implicit writeback would cause agent 10 to provide the requested datato agent 20 rather than the main memory unit 40.

[0007] In an implicit writeback, when agent 20 posts the request each ofthe other non-requesting agents performs an internal check to determinewhether it possesses a modified copy of the data at the requestedaddress in its internal cache system. If a non-requesting agent (agent10 in the example) does have a modified of the requested data in itsinternal cache system it so indicates in a cache coherency signal of thetransaction. The agent 10 drives the modified data on the externalcommunications bus 50. The requesting agent 20 and the main memory unit40 may read the data from the communications bus 50.

[0008] In almost all circumstances, explicit writebacks and implicitwritebacks can proceed concurrently in a multiple agent system withoutviolating cache coherency. Because explicit writebacks and implicitwritebacks are not acted upon immediately, but are often placed in apipeline of operations to be performed at a later time by an agent or acommunications bus, a problem in cache coherency can occur in theboundary condition when an agent initiates an implicit writeback fordata at a particular address while the agent is in the process ofperforming an explicit writeback of data from the same address. In thissituation, it is possible for the agent to report newly updated data tothe main memory unit via the implicit writeback before agent processesthe external writeback for the same address. Cache coherency would beviolated when the agent then processes the explicit writeback, becausethe explicit writeback will update memory with a copy of data from aparticular address that is not the most current copy.

[0009] In the prior art, the solution to this problem was to temporarilyhalt all explicit writebacks during the time an implicit writeback wasbeing processed. This suspension of all explicit writebacks resulted ina substantial performance loss, given that the probability that animplicit writeback and an explicit writeback involved data from the sameaddress, and thus that cache coherency would actually be compromised,was quite small.

[0010] Accordingly, there is a need in the art for a system and methodthat allows the performance of explicit writebacks to continue duringthe processing of implicit writebacks while still maintaining cachecoherency during the boundary condition where an agent initiates animplicit writeback for data at a particular address while the agent isin the process of performing an explicit writeback of data from the sameaddress.

SUMMARY

[0011] Embodiments of the present invention provide for a transactionmanagement method for a processing agent in which the agent receives arequest for data identified by an address. The agent then determineswhether it has in store a pending write transaction to the address and,if so, sets a transaction length associated with the pending writetransaction to zero.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 is a block diagram of a multiple agent system sharing amain memory unit over a communications bus in accordance with anembodiment of the present invention.

[0013]FIG. 2A is a more detailed block diagram of one of the agents inFIG. 1 in accordance with an embodiment of the present invention.

[0014]FIG. 2B is a still more detailed block diagram of the snoop queuecomponent of one of the agents in FIG. 1 in accordance with anembodiment of the present invention.

[0015]FIG. 3 is a flow diagram illustrating a method of operation of animplicit writeback in accordance with an embodiment of the presentinvention.

[0016]FIG. 4 is a flow diagram illustrating a method of operation of anexplicit writeback in accordance with an embodiment of the presentinvention.

DETAILED DESCRIPTION

[0017] The present invention provides for a system and method forallowing explicit writebacks to continue during snoop phases in amultiple agent system. Upon each incoming snoop request, the agentdetermines if the address of the snoop request matches an address ofdata within the agent. If there is a match, the agent copies the mostrecent data, changes the state of the data within the agent tounmodified, and transmits the copied data to the requesting agent andthe main memory unit. If the data resides in the external transactionqueue, the agent also changes the length of the data to zero.Additionally, prior to issuing each explicit writeback on thecommunications bus, an agent determines if the address of the explicitwriteback and any incoming snoop requests are the same. If there is amatch, the agent changes the data length of the explicit writeback tozero before transmitting the explicit writeback to the main memory unit.

[0018] In an embodiment, the principles of the present invention may beapplied in an agent 10 shown in FIG. 2A and FIG. 2B. As shown in FIG.2A, the agent 10 may include a bus sequencing unit (“BSU”) 150, a core130 and an internal cache 140. The BSU may include an internaltransaction queue (“ITQ”) 80, an external transaction queue (“ETQ”) 90,and a snoop queue (“SNPQ”) 110. An external bus controller (“EBC”) 100may interface the BSU 150 to the communications bus 50.

[0019] The internal cache 140 stores data in a plurality of cacheentries. It possesses logic responsive to a data request to determinewhether the internal cache 140 stores a valid copy of requested dataand, if so, it furnishes the requested data in response thereto.

[0020] The ITQ 80 receives and stores data requests issued by the agentcore 130. It coordinates with the internal cache 140 to determine if therequested data “hits” (can be furnished by) the internal cache 140. Ifnot, if a data request “misses” the internal cache 140, the ITQ 80forwards the data request to the ETQ 90. The ITQ 80 also coordinateswith the internal cache 140 to process explicit writebacks by passingalong data with a modified state to the ETQ 90 for eventual updating ofthe main memory unit 40. Such a process may be accomplished by eviction,wherein data with a modified state is evicted from a lower level of acache to higher level of a cache. Such an eviction may occur when thelower level of cache is full and space is required for more recent cacheentries.

[0021] The ETQ 90 interprets data requests and generates external bustransactions to fulfill them. The ETQ 90 is populated by several queueentries. The ETQ 90 manages the agent's transactions as they progress onthe external bus 50.

[0022] The snoop queue 110 causes cache coherency checks to be performedwithin the agent. Typically, in response to a new bus transaction issuedby another agent, the snoop queue 110 causes the generation of snoopprobes to various caches within the agent (such as internal cache 140)and to the ITQ 80 and ETQ 90. It receives responses to the snoop probesand generates snoop responses therefrom. If necessary, the snoop queue110 manages implicit writebacks of modified data from the agent.

[0023] The external bus controller 100 drives signals on the externalbus as commanded by the ETQ 90 and snoop queue 110.

[0024] As shown in FIG. 2B, the snoop queue 110 may include a pluralityof entries for the storage of data that may include an input 230, a datafield 240 and an address field 260. The data in the snoop queue may beassociated with the transactions of the snoop queue 110. Variousattributes in the snoop queue may be associated with the correspondingdata 240 and may contain information about such data including, forexample, the data's address 260 in the main memory unit 40.

[0025] The control logic 220 may, among other tasks, identify particulardata 240 based on the address field 260 of the data. The control logic220 may obtain this information using content addressable logic (“CAM”)210 in conjunction with the address field 260 and the input 230 fromother devices, using a method known in the art. The control logic 220may also alter the length field of the chosen data to zero in the ETQ90.

[0026] In an embodiment of the present invention, the agent 10 mayoperate in accordance with the method of FIG. 3 and FIG. 4 to allowexplicit writebacks to proceed during implicit writeback phases whilemaintaining cache coherency in the event that an explicit writeback isdirected to the same address as an incoming snoop phase.

[0027] As shown in FIG. 3 illustrating an embodiment of the presentinvention, the agent 10 may perform “snoop phases” when another agent20, 30 requests data at a specific address from the main memory unit 40over the communications bus 50 (Step 2010). The snoop queue 110 mayobserve transactions on the communications bus 50 via the external buscontroller 100. The snoop queue 110 may issue snoop probes to thevarious caches and transaction queues within the agent 10. Controlcircuitry within the caches and transaction queues return a hit flag anda copy of data if the cache or transaction queue stores modified data(Step 2020). If the snoop queue 110 finds that there is no modified datawith the same address as that of the request (Step 2030), the snoopqueue 110 issues a “miss” or “clean” snoop response on the external bus50 (Step 2080). The snoop phase then ends for the agent 10 (Step 2090).

[0028] If the snoop queue 110 finds that there is an address match in aline containing modified data within the agent 10 (Step 2030), the snoopqueue 110 proceeds to perform an implicit writeback. Among otheroperations, the snoop queue copies the data from the appropriatelocation in the agent 10 if the data is not in the ITQ 80 or ETQ 90(Step 2040), changes the state of the data in the agent 10 to unmodified(Step 2050), and changes the data length attribute of the data in theagent 10 to a length of zero if the data is in the ITQ 80 or the ETQ 90(Step 2060). The snoop queue 110 then reports that a match occurred tothe requesting agent 20, 30 over the communications bus 40 (Step 2070)and the snoop phase ends for the agent 10 (Step 2100). The snoop queue110 then transmits the copied data via an implicit writeback (Step2110). Such a transmission may use the external bus controller 100 tocommunicate with the other agents 20, 30 and the main memory unit 40 viathe communications bus 50.

[0029] To insure cache coherency, the snoop queue 110 changes the stateof the data in the agent 10 to an unmodified state (Step 2050) andchanges the length of the data in the agent 10 to zero if the data is inthe ITQ 80 or the ETQ 90 (Step 2060). These measures are necessary ifthis data is in a section of the agent 10, for example in the ETQ 90,where the data is awaiting to be transmitted to the communications bus50 via an explicit writeback. It is advantageous for the snoop queue 110to alter the data in such a way to nullify any effect of such apotential explicit writeback. Because the main memory unit 40 and theother agents 20, 30 will ignore any explicit writebacks with a datalength of zero, altering the data length attribute of the data to zerowill nullify the effect of an explicit writeback of this data. Oneadvantage of altering the data length to zero is that the ETQ 90 willprocess this nullified explicit writeback in the same manner as allother transactions. There is no need as in the prior art system toimpede the orderly processing of explicit writebacks in order tomaintain cache coherency.

[0030] As previously discussed, in order to maintain cache coherencywhile allowing explicit writebacks to continue during snoop phases, itis necessary to nullify the effect of those explicit writebacks of datawith the same address as any incoming, but not yet processed, snooprequests. As shown in FIG. 4 illustrating an embodiment of the presentinvention to accomplish this task, the ETQ 90 begins an explicitwriteback over the communications bus 50 (Step 1020). This stage of theexplicit writeback may include, for example, transmitting informationregarding the type of bus operation that is to performed, but does notinclude transmitting the data length of the explicit writeback. At thesame time or thereafter, but before the data length of the explicitwriteback is transmitted to the communications bus, the ETQ 90determines if the address of the explicit writeback matches the addressof an incoming snoop request (Step 1030). This may occur by, forexample, the ETQ 90 interfacing with the control logic 220 of the snoopqueue 110 via the input 230. The control logic 220 may then determine,possibly by use of content addressable logic, if any incoming snooprequests in the entries of the snoop queue 110 are for the same addressas the explicit writeback.

[0031] If the address of the explicit writeback does not match theaddress of an incoming snoop request (Step 1040), there is no cachecoherency problem and the ETQ 90 completes the explicit writeback in thenormal fashion (Steps 1050, 1060). If, however, the address of theexplicit writeback matches the address of an incoming snoop request,(Step 1040) the ETQ 90 changes the data length attribute of the data tozero (Step 1070) and then completes the explicit writeback with thisaltered parameter (Steps 1080, 1060). This will be effective innullifying the effect of this explicit writeback because the main memoryunit 40 and the other agents 20, 30 will ignore any explicit writebackswith a data length of zero. This nullified explicit writeback, however,may proceed in its normal fashion along with other, proper, explicitwritebacks. Moreover, the ETQ 90 does not alter the state of the datafrom its modified state. Accordingly, when the snoop queue 110 laterissues the matching snoop request, the snoop queue 110 will find themodified data with the matching address in the ETQ 90 and will performan implicit writeback using the most recently modified copy of data toupdate the main memory unit 40, as depicted in FIG. 3.

[0032] Accordingly, the present invention allows an agent to continueperforming explicit writebacks while concurrently processing snooprequests. The effect of explicit writebacks that would otherwise violatecache coherency is nullified by altering the data length attribute tozero of the offending explicit writeback. It will be appreciated bythose skilled in the art that the specific embodiments disclosed abovemay be readily utilized as a basis for modifying or designing othermethods and techniques for carrying out the same purposes of the presentinvention. It should also be realized by those skilled in the art thatsuch equivalent constructions do not depart from the spirit and scope ofthe invention as set forth in the following claims.

We claim:
 1. A transaction management method for a processing agent,comprising: receiving a request for data, the data identified by anaddress; determining whether there is a pending write transaction to theaddress; if so, altering the pending write transaction to nullify theeffect of the pending write transaction.
 2. The method of claim 1,wherein altering the pending write transaction comprises setting atransaction length associated with the pending write transaction tozero.
 3. The method of claim 2, further comprising setting a stateassociated with the pending write transaction to unmodified.
 4. Themethod of claim 3, further comprising posting the pending writetransaction.
 5. The method of claim 4, further comprising posting thezero transaction length associated with the pending write transaction.6. The method of claim 5, further comprising posting a second writetransaction identified by the same address as the pending writetransaction.
 7. The method of claim 6, further comprising posting anonzero transaction length associated with the second write transaction.8. The method of claim 4, wherein posting the pending write transactionincludes the use of an external bus controller.
 9. The method of claim2, wherein determining whether there is a pending write transaction tothe address includes the use of a cache.
 10. The method of claim 2,wherein receiving a request for data includes the use of an agent core.11. A transaction management method for a processing agent, comprising:prior to posting the length of a write transaction associated with anaddress, determining whether a request associated with the same addressis pending; if so, setting the transaction length of the writetransaction to zero and posting the transaction length information. 12.The method of claim 11, further comprising posting the writetransaction.
 13. The method of claim 11, wherein determining whether arequest associated with the same address is pending includes the use ofcontent addressable logic.
 14. The method of claim 11, wherein postingthe transaction length information includes the use of an external buscontroller.
 15. An agent, comprising: a transaction queue to store by aplurality of queue entries having fields associated with the address andstate of transactions; content addressable logic in association withaddress fields of the queue entries to nullify a pending writetransaction.
 16. The agent of claim 15 wherein said content addressablelogic is coupled to nullify the pending write transaction by setting atransaction length field to zero.
 17. The agent of claim 15, wherein thetransaction queue is adapted to setting the state associated with thewrite transaction to unmodified.